The present invention relates to digital circuits insensitized to external disturbances, especially to localized disturbances coming in particular from heavy ion bombardments.
Such a disturbance is likely to untimely switch the state of a memory point, and specific memory point structures must be adopted to overcome this disadvantage.
With past integrated circuit manufacturing technologies, a memory point was only likely to switch if the disturbance directly affected this memory point. For example, a heavy ion had to reach one of the transistors forming the memory point. Disturbances occurring outside of the memory points, that is, in combinatory logic circuits, had a very low probability of modifying the state of memory points. Indeed, such disturbances would translate as very short pulses, which would be practically filtered out by the high capacitances of the conductors. Even if such a disturbance caused a parasitic pulse reaching the input of a memory cell, this pulse had a low probability of modifying the state of the memory cell.
With recent technologies, the capacitances of conductors become smaller and smaller and the circuits, especially memory cells, react more and more rapidly, so that parasitic pulses caused by disturbances have sufficient durations to modify the memory cell state if they occur in the vicinity of an edge of a clock which clocks the memory cells.
Thus, if it is desired to insensitize a digital circuit of recent technology to localized disturbances, it is not enough to insensitize the memory points, but it must also be avoided for parasitic pulses that could be generated outside of the memory points to reach the memory points.
The generation of a parasitic pulse by a combinatory logic circuit can be considered as a mistake that could be corrected by a conventional solution.
FIG. 1 illustrates a conventional solution that could be used to correct errors generated by a combinatory logic circuit. It is a triple-redundancy error-correcting circuit. A same combinatory logic circuit 10 is duplicated twice, respectively at 11 and 12. The outputs of circuits 10 to 12 are provided to a majority vote circuit 14, which outputs the value which is provided by at least two of redundant circuits 10 to 12. The output of majority vote circuit 14 is thus error-free in case of a failure of at most one of redundant circuits 10 to 12, even if this failure is permanent.
Of course, this solution triples the silicon surface area of the integrated circuit.
There are other solutions, which consist of generating error-correcting codes for the outputs of a circuit. When all the outputs of a circuit are desired to be corrected, this solution is equivalent, in terms of surface area, to the triple redundancy of FIG. 1.